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RISC-V Patches for the 5.12 Merge Window

I have a handful of new RISC-V related patches for this merge window:
 
 * A check to ensure drivers are properly using uaccess.  This isn't
   manifesting with any of the drivers I'm currently using, but may catch
   errors in new drivers.
 * Some preliminary support for the FU740, along with the HiFive
   Unleashed it will appear on.
 * NUMA support for RISC-V, which involves making the arm64 code generic.
 * Support for kasan on the vmalloc region.
 * A handful of new drivers for the Kendryte K210, along with the DT
   plumbing required to boot on a handful of K210-based boards.
 * Support for allocating ASIDs.
 * Preliminary support for kernels larger than 128MiB.
 * Various other improvements to our KASAN support, including the
   utilization of huge pages when allocating the KASAN regions.
 
 We may have already found a bug with the KASAN_VMALLOC code, but it's
 passing my tests.  There's a fix in the works, but that will probably
 miss the merge window.
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Merge tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt:
 "A handful of new RISC-V related patches for this merge window:

   - A check to ensure drivers are properly using uaccess. This isn't
     manifesting with any of the drivers I'm currently using, but may
     catch errors in new drivers.

   - Some preliminary support for the FU740, along with the HiFive
     Unleashed it will appear on.

   - NUMA support for RISC-V, which involves making the arm64 code
     generic.

   - Support for kasan on the vmalloc region.

   - A handful of new drivers for the Kendryte K210, along with the DT
     plumbing required to boot on a handful of K210-based boards.

   - Support for allocating ASIDs.

   - Preliminary support for kernels larger than 128MiB.

   - Various other improvements to our KASAN support, including the
     utilization of huge pages when allocating the KASAN regions.

  We may have already found a bug with the KASAN_VMALLOC code, but it's
  passing my tests. There's a fix in the works, but that will probably
  miss the merge window.

* tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (75 commits)
  riscv: Improve kasan population by using hugepages when possible
  riscv: Improve kasan population function
  riscv: Use KASAN_SHADOW_INIT define for kasan memory initialization
  riscv: Improve kasan definitions
  riscv: Get rid of MAX_EARLY_MAPPING_SIZE
  soc: canaan: Sort the Makefile alphabetically
  riscv: Disable KSAN_SANITIZE for vDSO
  riscv: Remove unnecessary declaration
  riscv: Add Canaan Kendryte K210 SD card defconfig
  riscv: Update Canaan Kendryte K210 defconfig
  riscv: Add Kendryte KD233 board device tree
  riscv: Add SiPeed MAIXDUINO board device tree
  riscv: Add SiPeed MAIX GO board device tree
  riscv: Add SiPeed MAIX DOCK board device tree
  riscv: Add SiPeed MAIX BiT board device tree
  riscv: Update Canaan Kendryte K210 device tree
  dt-bindings: add resets property to dw-apb-timer
  dt-bindings: fix sifive gpio properties
  dt-bindings: update sifive uart compatible string
  dt-bindings: update sifive clint compatible string
  ...
master
Linus Torvalds 2 months ago
parent
commit
8b83369ddc
121 changed files with 7605 additions and 1040 deletions
  1. +25
    -4
      Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
  2. +8
    -5
      Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
  3. +109
    -0
      Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml
  4. +171
    -0
      Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml
  5. +6
    -3
      Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
  6. +40
    -0
      Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml
  7. +47
    -0
      Documentation/devicetree/bindings/riscv/canaan.yaml
  8. +8
    -0
      Documentation/devicetree/bindings/riscv/cpus.yaml
  9. +30
    -4
      Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
  10. +12
    -5
      Documentation/devicetree/bindings/riscv/sifive.yaml
  11. +1
    -0
      Documentation/devicetree/bindings/serial/sifive-serial.yaml
  12. +8
    -4
      Documentation/devicetree/bindings/timer/sifive,clint.yaml
  13. +3
    -0
      Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
  14. +23
    -0
      MAINTAINERS
  15. +1
    -0
      arch/arm64/Kconfig
  16. +1
    -47
      arch/arm64/include/asm/numa.h
  17. +0
    -12
      arch/arm64/kernel/acpi_numa.c
  18. +0
    -1
      arch/arm64/mm/Makefile
  19. +2
    -2
      arch/arm64/mm/init.c
  20. +46
    -2
      arch/riscv/Kconfig
  21. +22
    -11
      arch/riscv/Kconfig.socs
  22. +13
    -1
      arch/riscv/Makefile
  23. +1
    -1
      arch/riscv/boot/dts/Makefile
  24. +5
    -0
      arch/riscv/boot/dts/canaan/Makefile
  25. +152
    -0
      arch/riscv/boot/dts/canaan/canaan_kd233.dts
  26. +459
    -0
      arch/riscv/boot/dts/canaan/k210.dtsi
  27. +46
    -0
      arch/riscv/boot/dts/canaan/k210_generic.dts
  28. +209
    -0
      arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
  29. +211
    -0
      arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
  30. +219
    -0
      arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
  31. +184
    -0
      arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
  32. +0
    -4
      arch/riscv/boot/dts/kendryte/Makefile
  33. +0
    -23
      arch/riscv/boot/dts/kendryte/k210.dts
  34. +0
    -125
      arch/riscv/boot/dts/kendryte/k210.dtsi
  35. +2
    -1
      arch/riscv/boot/dts/sifive/Makefile
  36. +293
    -0
      arch/riscv/boot/dts/sifive/fu740-c000.dtsi
  37. +253
    -0
      arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
  38. +37
    -9
      arch/riscv/configs/nommu_k210_defconfig
  39. +92
    -0
      arch/riscv/configs/nommu_k210_sdcard_defconfig
  40. +1
    -0
      arch/riscv/include/asm/bug.h
  41. +6
    -0
      arch/riscv/include/asm/csr.h
  42. +19
    -3
      arch/riscv/include/asm/kasan.h
  43. +40
    -0
      arch/riscv/include/asm/kprobes.h
  44. +2
    -0
      arch/riscv/include/asm/mmu.h
  45. +10
    -0
      arch/riscv/include/asm/mmu_context.h
  46. +13
    -0
      arch/riscv/include/asm/mmzone.h
  47. +8
    -0
      arch/riscv/include/asm/numa.h
  48. +0
    -3
      arch/riscv/include/asm/page.h
  49. +14
    -0
      arch/riscv/include/asm/pci.h
  50. +21
    -0
      arch/riscv/include/asm/pgtable.h
  51. +24
    -0
      arch/riscv/include/asm/probes.h
  52. +1
    -0
      arch/riscv/include/asm/processor.h
  53. +35
    -0
      arch/riscv/include/asm/ptrace.h
  54. +7
    -11
      arch/riscv/include/asm/sbi.h
  55. +1
    -1
      arch/riscv/include/asm/set_memory.h
  56. +0
    -38
      arch/riscv/include/asm/soc.h
  57. +2
    -1
      arch/riscv/include/asm/stackprotector.h
  58. +2
    -0
      arch/riscv/include/asm/stacktrace.h
  59. +3
    -1
      arch/riscv/include/asm/thread_info.h
  60. +40
    -0
      arch/riscv/include/asm/uprobes.h
  61. +4
    -2
      arch/riscv/kernel/Makefile
  62. +3
    -0
      arch/riscv/kernel/asm-offsets.c
  63. +50
    -45
      arch/riscv/kernel/ftrace.c
  64. +4
    -0
      arch/riscv/kernel/head.S
  65. +1
    -1
      arch/riscv/kernel/image-vars.h
  66. +152
    -190
      arch/riscv/kernel/mcount-dyn.S
  67. +6
    -2
      arch/riscv/kernel/patch.c
  68. +6
    -0
      arch/riscv/kernel/probes/Makefile
  69. +48
    -0
      arch/riscv/kernel/probes/decode-insn.c
  70. +18
    -0
      arch/riscv/kernel/probes/decode-insn.h
  71. +53
    -0
      arch/riscv/kernel/probes/ftrace.c
  72. +398
    -0
      arch/riscv/kernel/probes/kprobes.c
  73. +93
    -0
      arch/riscv/kernel/probes/kprobes_trampoline.S
  74. +85
    -0
      arch/riscv/kernel/probes/simulate-insn.c
  75. +47
    -0
      arch/riscv/kernel/probes/simulate-insn.h
  76. +186
    -0
      arch/riscv/kernel/probes/uprobes.c
  77. +15
    -3
      arch/riscv/kernel/process.c
  78. +99
    -0
      arch/riscv/kernel/ptrace.c
  79. +17
    -19
      arch/riscv/kernel/sbi.c
  80. +18
    -5
      arch/riscv/kernel/setup.c
  81. +3
    -0
      arch/riscv/kernel/signal.c
  82. +11
    -1
      arch/riscv/kernel/smpboot.c
  83. +0
    -27
      arch/riscv/kernel/soc.c
  84. +17
    -5
      arch/riscv/kernel/stacktrace.c
  85. +21
    -1
      arch/riscv/kernel/traps.c
  86. +2
    -1
      arch/riscv/kernel/vdso/Makefile
  87. +2
    -0
      arch/riscv/lib/Makefile
  88. +10
    -0
      arch/riscv/lib/error-inject.c
  89. +2
    -1
      arch/riscv/mm/Makefile
  90. +261
    -4
      arch/riscv/mm/context.c
  91. +32
    -6
      arch/riscv/mm/fault.c
  92. +27
    -81
      arch/riscv/mm/init.c
  93. +145
    -31
      arch/riscv/mm/kasan_init.c
  94. +6
    -0
      drivers/base/Kconfig
  95. +1
    -0
      drivers/base/Makefile
  96. +30
    -10
      drivers/base/arch_numa.c
  97. +7
    -0
      drivers/clk/Kconfig
  98. +1
    -0
      drivers/clk/Makefile
  99. +1007
    -0
      drivers/clk/clk-k210.c
  100. +13
    -0
      drivers/pinctrl/Kconfig

+ 25
- 4
Documentation/devicetree/bindings/gpio/sifive,gpio.yaml View File

@ -13,7 +13,10 @@ maintainers:
properties:
compatible:
items:
- const: sifive,fu540-c000-gpio
- enum:
- sifive,fu540-c000-gpio
- sifive,fu740-c000-gpio
- canaan,k210-gpiohs
- const: sifive,gpio0
reg:
@ -21,9 +24,9 @@ properties:
interrupts:
description:
interrupt mapping one per GPIO. Maximum 16 GPIOs.
Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
minItems: 1
maxItems: 16
maxItems: 32
interrupt-controller: true
@ -36,6 +39,14 @@ properties:
"#gpio-cells":
const: 2
ngpios:
description:
The number of GPIOs available on the controller implementation.
It is 16 for the SiFive SoCs and 32 for the Canaan K210.
minimum: 1
maximum: 32
default: 16
gpio-controller: true
required:
@ -44,10 +55,20 @@ required:
- interrupts
- interrupt-controller
- "#interrupt-cells"
- clocks
- "#gpio-cells"
- gpio-controller
if:
properties:
compatible:
contains:
enum:
- sifive,fu540-c000-gpio
- sifive,fu740-c000-gpio
then:
required:
- clocks
additionalProperties: false
examples:


+ 8
- 5
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml View File

@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Platform-Level Interrupt Controller (PLIC)
description:
SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
(PLIC) high-level specification in the RISC-V Privileged Architecture
specification. The PLIC connects all external interrupts in the system to all
hart contexts in the system, via the external interrupt source in each hart.
SiFive SoCs and other RISC-V SoCs include an implementation of the
Platform-Level Interrupt Controller (PLIC) high-level specification in
the RISC-V Privileged Architecture specification. The PLIC connects all
external interrupts in the system to all hart contexts in the system, via
the external interrupt source in each hart.
A hart context is a privilege mode in a hardware execution thread. For example,
in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
@ -42,7 +43,9 @@ maintainers:
properties:
compatible:
items:
- const: sifive,fu540-c000-plic
- enum:
- sifive,fu540-c000-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
reg:


+ 109
- 0
Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml View File

@ -0,0 +1,109 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan Kendryte K210 System Controller Device Tree Bindings
maintainers:
- Damien Le Moal <damien.lemoal@wdc.com>
description:
Canaan Inc. Kendryte K210 SoC system controller which provides a
register map for controlling the clocks, reset signals and pin power
domains of the SoC.
properties:
compatible:
items:
- const: canaan,k210-sysctl
- const: syscon
- const: simple-mfd
clocks:
maxItems: 1
description:
System controller Advanced Power Bus (APB) interface clock source.
clock-names:
items:
- const: pclk
reg:
maxItems: 1
clock-controller:
# Child node
type: object
$ref: "../clock/canaan,k210-clk.yaml"
description:
Clock controller for the SoC clocks. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml.
reset-controller:
# Child node
type: object
$ref: "../reset/canaan,k210-rst.yaml"
description:
Reset controller for the SoC. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml.
syscon-reboot:
# Child node
type: object
$ref: "../power/reset/syscon-reboot.yaml"
description:
Reboot method for the SoC. This child node definition
should follow the bindings specified in
Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml.
required:
- compatible
- clocks
- reg
- clock-controller
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/k210-clk.h>
#include <dt-bindings/reset/k210-rst.h>
clocks {
in0: oscllator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
};
sysctl: syscon@50440000 {
compatible = "canaan,k210-sysctl",
"syscon", "simple-mfd";
reg = <0x50440000 0x100>;
clocks = <&sysclk K210_CLK_APB1>;
clock-names = "pclk";
sysclk: clock-controller {
#clock-cells = <1>;
compatible = "canaan,k210-clk";
clocks = <&in0>;
};
sysrst: reset-controller {
compatible = "canaan,k210-rst";
#reset-cells = <1>;
};
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&sysctl>;
offset = <48>;
mask = <1>;
value = <1>;
};
};

+ 171
- 0
Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml View File

@ -0,0 +1,171 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan Kendryte K210 FPIOA Device Tree Bindings
maintainers:
- Damien Le Moal <damien.lemoal@wdc.com>
description:
The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA)
controller allows assiging any of 256 possible functions to any of
48 IO pins of the SoC. Pin function configuration is performed on
a per-pin basis.
properties:
compatible:
const: canaan,k210-fpioa
reg:
maxItems: 1
description:
Address and length of the register set for the FPIOA controller.
clocks:
items:
- description: Controller reference clock source
- description: APB interface clock source
clock-names:
items:
- const: ref
- const: pclk
resets:
maxItems: 1
canaan,k210-sysctl-power:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: |
phandle of the K210 system controller node and offset of its
power domain control register.
patternProperties:
'-pinmux$':
type: object
$ref: /schemas/pinctrl/pinmux-node.yaml
description:
FPIOA client devices use sub-nodes to define the desired pin
configuration. Client device sub-nodes use the pinux property
below.
properties:
pinmux:
description:
List of IO pins alternate functions. The values for each IO
pin is a combination of an IO pin number (0 to 47) with the
desired function for the IO pin. Functions are defined as
macros in include/dt-bindings/pinctrl/k210-fpioa.h.
The K210_FPIOA(IO pin, function) macro is provided to
facilitate the combination of IO pin numbers and functions.
required:
- pinmux
additionalProperties: false
'-pins$':
type: object
$ref: /schemas/pinctrl/pincfg-node.yaml
description:
FPIOA client devices use sub-nodes to define the desired
configuration of pins. Client device sub-nodes use the
properties below.
properties:
pins:
description:
List of IO pins affected by the properties specified in this
subnode. IO pins are identified using the pin names "IO_xx".
Pin configuration nodes can also define the power domain to
be used for the SoC pin groups A0 (IO pins 0-5),
A1 (IO pins 6-11), A2 (IO pins 12-17), B0 (IO pins 18-23),
B1 (IO pins 24-29), B2 (IO pins 30-35), B3 (IO pins 30-35),
C0 (IO pins 36-41) and C1 (IO pins 42-47) using the
power-source property.
items:
anyOf:
- pattern: "^(IO_([0-9]*))|(A[0-2])|(B[3-5])|(C[6-7])$"
- enum: [ IO_0, IO_1, IO_2, IO_3, IO_4, IO_5, IO_6, IO_7,
IO_8, IO_9, IO_10, IO_11, IO_12, IO_13, IO_14,
IO_15, IO_16, IO_17, IO_18, IO_19, IO_20, IO_21,
IO_22, IO_23, IO_24, IO_25, IO_26, IO_27, IO_28,
IO_29, IO_30, IO_31, IO_32, IO_33, IO_34, IO_35,
IO_36, IO_37, IO_38, IO_39, IO_40, IO_41, IO_42,
IO_43, IO_44, IO_45, IO_46, IO_47,
A0, A1, A2, B3, B4, B5, C6, C7 ]
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength: true
drive-strength-microamp: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
input-polarity-invert:
description:
Enable or disable pin input polarity inversion.
output-enable: true
output-disable: true
output-high: true
output-low: true
output-polarity-invert:
description:
Enable or disable pin output polarity inversion.
slew-rate: true
power-source: true
additionalProperties: false
required:
- compatible
- reg
- clocks
- canaan,k210-sysctl-power
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/k210-fpioa.h>
#include <dt-bindings/clock/k210-clk.h>
#include <dt-bindings/reset/k210-rst.h>
fpioa: pinmux@502B0000 {
compatible = "canaan,k210-fpioa";
reg = <0x502B0000 0x100>;
clocks = <&sysclk K210_CLK_FPIOA>,
<&sysclk K210_CLK_APB0>;
clock-names = "ref", "pclk";
resets = <&sysrst K210_RST_FPIOA>;
canaan,k210-sysctl-power = <&sysctl 108>;
pinctrl-0 = <&jtag_pinctrl>;
pinctrl-names = "default";
jtag_pinctrl: jtag-pinmux {
pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
<K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
<K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
<K210_FPIOA(3, K210_PCF_JTAG_TDO)>;
};
};

+ 6
- 3
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml View File

@ -25,12 +25,15 @@ description:
properties:
compatible:
items:
- const: sifive,fu540-c000-pwm
- enum:
- sifive,fu540-c000-pwm
- sifive,fu740-c000-pwm
- const: sifive,pwm0
description:
Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
compatible strings are "sifive,fu540-c000-pwm" and
"sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
SiFive PWM v0 IP block with no chip integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details.


+ 40
- 0
Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml View File

@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/canaan,k210-rst.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan Kendryte K210 Reset Controller Device Tree Bindings
maintainers:
- Damien Le Moal <damien.lemoal@wdc.com>
description: |
Canaan Kendryte K210 reset controller driver which supports the SoC
system controller supplied reset registers for the various peripherals
of the SoC. The K210 reset controller node must be defined as a child
node of the K210 system controller node.
See also:
- dt-bindings/reset/k210-rst.h
properties:
compatible:
const: canaan,k210-rst
'#reset-cells':
const: 1
required:
- '#reset-cells'
- compatible
additionalProperties: false
examples:
- |
#include <dt-bindings/reset/k210-rst.h>
sysrst: reset-controller {
compatible = "canaan,k210-rst";
#reset-cells = <1>;
};

+ 47
- 0
Documentation/devicetree/bindings/riscv/canaan.yaml View File

@ -0,0 +1,47 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/riscv/canaan.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Canaan SoC-based boards
maintainers:
- Damien Le Moal <damien.lemoal@wdc.com>
description:
Canaan Kendryte K210 SoC-based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- const: sipeed,maix-bit
- const: sipeed,maix-bitm
- const: canaan,kendryte-k210
- items:
- const: sipeed,maix-go
- const: canaan,kendryte-k210
- items:
- const: sipeed,maix-dock-m1
- const: sipeed,maix-dock-m1w
- const: canaan,kendryte-k210
- items:
- const: sipeed,maixduino
- const: canaan,kendryte-k210
- items:
- const: canaan,kendryte-kd233
- const: canaan,kendryte-k210
- items:
- const: canaan,kendryte-k210
additionalProperties: true
...

+ 8
- 0
Documentation/devicetree/bindings/riscv/cpus.yaml View File

@ -28,11 +28,18 @@ properties:
- items:
- enum:
- sifive,rocket0
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e51
- sifive,e71
- sifive,u54-mc
- sifive,u74-mc
- sifive,u54
- sifive,u74
- sifive,u5
- sifive,u7
- canaan,k210
- const: riscv
- const: riscv # Simulator only
description:
@ -50,6 +57,7 @@ properties:
- riscv,sv32
- riscv,sv39
- riscv,sv48
- riscv,none
riscv,isa:
description:


+ 30
- 4
Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml View File

@ -27,6 +27,7 @@ select:
items:
- enum:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
required:
- compatible
@ -34,7 +35,9 @@ select:
properties:
compatible:
items:
- const: sifive,fu540-c000-ccache
- enum:
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
- const: cache
cache-block-size:
@ -52,10 +55,13 @@ properties:
cache-unified: true
interrupts:
description: |
Must contain entries for DirError, DataError and DataFail signals.
minItems: 3
maxItems: 3
maxItems: 4
items:
- description: DirError interrupt
- description: DataError interrupt
- description: DataFail interrupt
- description: DirFail interrupt
reg:
maxItems: 1
@ -68,6 +74,26 @@ properties:
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
if:
properties:
compatible:
contains:
const: sifive,fu540-c000-ccache
then:
properties:
interrupts:
description: |
Must contain entries for DirError, DataError and DataFail signals.
maxItems: 3
else:
properties:
interrupts:
description: |
Must contain entries for DirError, DataError, DataFail, DirFail signals.
minItems: 4
additionalProperties: false
required:


+ 12
- 5
Documentation/devicetree/bindings/riscv/sifive.yaml View File

@ -17,11 +17,18 @@ properties:
$nodename:
const: '/'
compatible:
items:
- enum:
- sifive,hifive-unleashed-a00
- const: sifive,fu540-c000
- const: sifive,fu540
oneOf:
- items:
- enum:
- sifive,hifive-unleashed-a00
- const: sifive,fu540-c000
- const: sifive,fu540
- items:
- enum:
- sifive,hifive-unmatched-a00
- const: sifive,fu740-c000
- const: sifive,fu740
additionalProperties: true


+ 1
- 0
Documentation/devicetree/bindings/serial/sifive-serial.yaml View File

@ -20,6 +20,7 @@ properties:
- enum:
- sifive,fu540-c000-uart
- sifive,fu740-c000-uart
- canaan,k210-uarths
- const: sifive,uart0
description:


+ 8
- 4
Documentation/devicetree/bindings/timer/sifive,clint.yaml View File

@ -23,15 +23,19 @@ description:
properties:
compatible:
items:
- const: sifive,fu540-c000-clint
- enum:
- sifive,fu540-c000-clint
- canaan,k210-clint
- const: sifive,clint0
description:
Should be "sifive,<chip>-clint" and "sifive,clint<version>".
Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
Supported compatible strings are -
"sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive
CLINT v0 IP block with no chip integration tweaks.
onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and
"sifive,clint0" for the SiFive CLINT v0 IP block with no chip
integration tweaks.
Please refer to sifive-blocks-ip-versioning.txt for details
reg:


+ 3
- 0
Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml View File

@ -24,6 +24,9 @@ properties:
interrupts:
maxItems: 1
resets:
maxItems: 1
clocks:
minItems: 1
items:


+ 23
- 0
MAINTAINERS View File

@ -3855,6 +3855,29 @@ W: https://github.com/Cascoda/ca8210-linux.git
F: Documentation/devicetree/bindings/net/ieee802154/ca8210.txt
F: drivers/net/ieee802154/ca8210.c
CANAAN/KENDRYTE K210 SOC FPIOA DRIVER
M: Damien Le Moal <damien.lemoal@wdc.com>
L: linux-riscv@lists.infradead.org
L: linux-gpio@vger.kernel.org (pinctrl driver)
F: Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml
F: drivers/pinctrl/pinctrl-k210.c
CANAAN/KENDRYTE K210 SOC RESET CONTROLLER DRIVER
M: Damien Le Moal <damien.lemoal@wdc.com>
L: linux-kernel@vger.kernel.org
L: linux-riscv@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml
F: drivers/reset/reset-k210.c
CANAAN/KENDRYTE K210 SOC SYSTEM CONTROLLER DRIVER
M: Damien Le Moal <damien.lemoal@wdc.com>
L: linux-riscv@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/mfd/canaan,k210-sysctl.yaml
F: drivers/soc/canaan/
F: include/soc/canaan/
CACHEFILES: FS-CACHE BACKEND FOR CACHING ON MOUNTED FILESYSTEMS
M: David Howells <dhowells@redhat.com>
L: linux-cachefs@redhat.com (moderated for non-subscribers)


+ 1
- 0
arch/arm64/Kconfig View File

@ -999,6 +999,7 @@ config HOTPLUG_CPU
# Common NUMA Features
config NUMA
bool "NUMA Memory Allocation and Scheduler Support"
select GENERIC_ARCH_NUMA
select ACPI_NUMA if ACPI
select OF_NUMA
help


+ 1
- 47
arch/arm64/include/asm/numa.h View File

@ -3,52 +3,6 @@
#define __ASM_NUMA_H
#include <asm/topology.h>
#ifdef CONFIG_NUMA
#define NR_NODE_MEMBLKS (MAX_NUMNODES * 2)
int __node_distance(int from, int to);
#define node_distance(a, b) __node_distance(a, b)
extern nodemask_t numa_nodes_parsed __initdata;
extern bool numa_off;
/* Mappings between node number and cpus on that node. */
extern cpumask_var_t node_to_cpumask_map[MAX_NUMNODES];
void numa_clear_node(unsigned int cpu);
#ifdef CONFIG_DEBUG_PER_CPU_MAPS
const struct cpumask *cpumask_of_node(int node);
#else
/* Returns a pointer to the cpumask of CPUs on Node 'node'. */
static inline const struct cpumask *cpumask_of_node(int node)
{
if (node == NUMA_NO_NODE)
return cpu_all_mask;
return node_to_cpumask_map[node];
}
#endif
void __init arm64_numa_init(void);
int __init numa_add_memblk(int nodeid, u64 start, u64 end);
void __init numa_set_distance(int from, int to, int distance);
void __init numa_free_distance(void);
void __init early_map_cpu_to_node(unsigned int cpu, int nid);
void numa_store_cpu_info(unsigned int cpu);
void numa_add_cpu(unsigned int cpu);
void numa_remove_cpu(unsigned int cpu);
#else /* CONFIG_NUMA */
static inline void numa_store_cpu_info(unsigned int cpu) { }
static inline void numa_add_cpu(unsigned int cpu) { }
static inline void numa_remove_cpu(unsigned int cpu) { }
static inline void arm64_numa_init(void) { }
static inline void early_map_cpu_to_node(unsigned int cpu, int nid) { }
#endif /* CONFIG_NUMA */
#include <asm-generic/numa.h>
#endif /* __ASM_NUMA_H */

+ 0
- 12
arch/arm64/kernel/acpi_numa.c View File

@ -118,15 +118,3 @@ void __init acpi_numa_gicc_affinity_init(struct acpi_srat_gicc_affinity *pa)
node_set(node, numa_nodes_parsed);
}
int __init arm64_acpi_numa_init(void)
{
int ret;
ret = acpi_numa_init();
if (ret) {
pr_info("Failed to initialise from firmware\n");
return ret;
}
return srat_disabled() ? -EINVAL : 0;
}

+ 0
- 1
arch/arm64/mm/Makefile View File

@ -7,7 +7,6 @@ obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
obj-$(CONFIG_PTDUMP_CORE) += ptdump.o
obj-$(CONFIG_PTDUMP_DEBUGFS) += ptdump_debugfs.o
obj-$(CONFIG_TRANS_TABLE) += trans_pgd.o
obj-$(CONFIG_NUMA) += numa.o
obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
obj-$(CONFIG_ARM64_MTE) += mteswap.o
KASAN_SANITIZE_physaddr.o += n


+ 2
- 2
arch/arm64/mm/init.c View File

@ -416,10 +416,10 @@ void __init bootmem_init(void)
max_pfn = max_low_pfn = max;
min_low_pfn = min;
arm64_numa_init();
arch_numa_init();
/*
* must be done after arm64_numa_init() which calls numa_init() to
* must be done after arch_numa_init() which calls numa_init() to
* initialize node_online_map that gets used in hugetlb_cma_reserve()
* while allocating required CMA size across online nodes.
*/


+ 46
- 2
arch/riscv/Kconfig View File

@ -57,6 +57,7 @@ config RISCV
select HAVE_ARCH_JUMP_LABEL
select HAVE_ARCH_JUMP_LABEL_RELATIVE
select HAVE_ARCH_KASAN if MMU && 64BIT
select HAVE_ARCH_KASAN_VMALLOC if MMU && 64BIT
select HAVE_ARCH_KGDB
select HAVE_ARCH_KGDB_QXFER_PKT
select HAVE_ARCH_MMAP_RND_BITS if MMU
@ -67,14 +68,19 @@ config RISCV
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_CONTIGUOUS if MMU
select HAVE_EBPF_JIT if MMU
select HAVE_FUNCTION_ERROR_INJECTION
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_GCC_PLUGINS
select HAVE_GENERIC_VDSO if MMU && 64BIT
select HAVE_IRQ_TIME_ACCOUNTING
select HAVE_KPROBES
select HAVE_KPROBES_ON_FTRACE
select HAVE_KRETPROBES
select HAVE_PCI
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
select HAVE_PERF_USER_STACK_DUMP
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_STACKPROTECTOR
select HAVE_SYSCALL_TRACEPOINTS
select IRQ_DOMAIN
@ -143,7 +149,7 @@ config PAGE_OFFSET
default 0xffffffe000000000 if 64BIT && MAXPHYSMEM_128GB
config ARCH_FLATMEM_ENABLE
def_bool y
def_bool !NUMA
config ARCH_SPARSEMEM_ENABLE
def_bool y
@ -156,6 +162,9 @@ config ARCH_SELECT_MEMORY_MODEL
config ARCH_WANT_GENERAL_HUGETLB
def_bool y
config ARCH_SUPPORTS_UPROBES
def_bool y
config SYS_SUPPORTS_HUGETLBFS
depends on MMU
def_bool y
@ -302,6 +311,35 @@ config TUNE_GENERIC
endchoice
# Common NUMA Features
config NUMA
bool "NUMA Memory Allocation and Scheduler Support"
select GENERIC_ARCH_NUMA
select OF_NUMA
select ARCH_SUPPORTS_NUMA_BALANCING
help
Enable NUMA (Non-Uniform Memory Access) support.
The kernel will try to allocate memory used by a CPU on the
local memory of the CPU and add some more NUMA awareness to the kernel.
config NODES_SHIFT
int "Maximum NUMA Nodes (as a power of 2)"
range 1 10
default "2"
depends on NEED_MULTIPLE_NODES
help
Specify the maximum number of NUMA Nodes available on the target
system. Increases memory reserved to accommodate various tables.
config USE_PERCPU_NUMA_NODE_ID
def_bool y
depends on NUMA
config NEED_PER_CPU_EMBED_FIRST_CHUNK
def_bool y
depends on NUMA
config RISCV_ISA_C
bool "Emit compressed instructions when building Linux"
default y
@ -416,11 +454,17 @@ config EFI
allow the kernel to be booted as an EFI application. This
is only useful on systems that have UEFI firmware.
config CC_HAVE_STACKPROTECTOR_TLS
def_bool $(cc-option,-mstack-protector-guard=tls -mstack-protector-guard-reg=tp -mstack-protector-guard-offset=0)
config STACKPROTECTOR_PER_TASK
def_bool y
depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS
endmenu
config BUILTIN_DTB
def_bool n
depends on RISCV_M_MODE
depends on OF
menu "Power management options"


+ 22
- 11
arch/riscv/Kconfig.socs View File

@ -22,30 +22,41 @@ config SOC_VIRT
help
This enables support for QEMU Virt Machine.
config SOC_KENDRYTE
bool "Kendryte K210 SoC"
config SOC_CANAAN
bool "Canaan Kendryte K210 SoC"
depends on !MMU
select CLINT_TIMER if RISCV_M_MODE
select SERIAL_SIFIVE if TTY
select SERIAL_SIFIVE_CONSOLE if TTY
select SIFIVE_PLIC
select ARCH_HAS_RESET_CONTROLLER
select PINCTRL
help
This enables support for Kendryte K210 SoC platform hardware.
This enables support for Canaan Kendryte K210 SoC platform hardware.
config SOC_KENDRYTE_K210_DTB
def_bool y
depends on SOC_KENDRYTE_K210_DTB_BUILTIN
if SOC_CANAAN
config SOC_KENDRYTE_K210_DTB_BUILTIN
bool "Builtin device tree for the Kendryte K210"
depends on SOC_KENDRYTE
config SOC_CANAAN_K210_DTB_BUILTIN
bool "Builtin device tree for the Canaan Kendryte K210"
depends on SOC_CANAAN
default y
select OF
select BUILTIN_DTB
select SOC_KENDRYTE_K210_DTB
help
Builds a device tree for the Kendryte K210 into the Linux image.
Build a device tree for the Kendryte K210 into the Linux image.
This option should be selected if no bootloader is being used.
If unsure, say Y.
config SOC_CANAAN_K210_DTB_SOURCE
string "Source file for the Canaan Kendryte K210 builtin DTB"
depends on SOC_CANAAN
depends on SOC_CANAAN_K210_DTB_BUILTIN
default "k210_generic"
help
Base name (without suffix, relative to arch/riscv/boot/dts/canaan)
for the DTS file that will be used to produce the DTB linked into the
kernel.
endif
endmenu

+ 13
- 1
arch/riscv/Makefile View File

@ -12,6 +12,8 @@ OBJCOPYFLAGS := -O binary
LDFLAGS_vmlinux :=
ifeq ($(CONFIG_DYNAMIC_FTRACE),y)
LDFLAGS_vmlinux := --no-relax
KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
CC_FLAGS_FTRACE := -fpatchable-function-entry=8
endif
ifeq ($(CONFIG_64BIT)$(CONFIG_CMODEL_MEDLOW),yy)
@ -65,6 +67,16 @@ KBUILD_CFLAGS_MODULE += $(call cc-option,-mno-relax)
# architectures. It's faster to have GCC emit only aligned accesses.
KBUILD_CFLAGS += $(call cc-option,-mstrict-align)
ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y)
prepare: stack_protector_prepare
stack_protector_prepare: prepare0
$(eval KBUILD_CFLAGS += -mstack-protector-guard=tls \
-mstack-protector-guard-reg=tp \
-mstack-protector-guard-offset=$(shell \
awk '{if ($$2 == "TSK_STACK_CANARY") print $$3;}' \
include/generated/asm-offsets.h))
endif
# arch specific predefines for sparse
CHECKFLAGS += -D__riscv -D__riscv_xlen=$(BITS)
@ -83,7 +95,7 @@ PHONY += vdso_install
vdso_install:
$(Q)$(MAKE) $(build)=arch/riscv/kernel/vdso $@
ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_KENDRYTE),yy)
ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN),yy)
KBUILD_IMAGE := $(boot)/loader.bin
else
KBUILD_IMAGE := $(boot)/Image.gz


+ 1
- 1
arch/riscv/boot/dts/Makefile View File

@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += sifive
subdir-y += kendryte
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))

+ 5
- 0
arch/riscv/boot/dts/canaan/Makefile View File

@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
ifneq ($(CONFIG_SOC_CANAAN_K210_DTB_SOURCE),"")
dtb-y += $(strip $(shell echo $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE))).dtb
obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .o, $(dtb-y))
endif

+ 152
- 0
arch/riscv/boot/dts/canaan/canaan_kd233.dts View File

@ -0,0 +1,152 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
* Copyright (C) 2020 Western Digital Corporation or its affiliates.
*/
/dts-v1/;
#include "k210.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Kendryte KD233";
compatible = "canaan,kendryte-kd233", "canaan,kendryte-k210";
chosen {
bootargs = "earlycon console=ttySIF0";
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
led0 {
gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
};
led1 {
gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
};
};
gpio-keys {
compatible = "gpio-keys";
key0 {
label = "KEY0";
linux,code = <BTN_0>;
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
};
};
};
&fpioa {
pinctrl-0 = <&jtag_pinctrl>;
pinctrl-names = "default";
status = "okay";
jtag_pinctrl: jtag-pinmux {
pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
<K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
<K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
<K210_FPIOA(3, K210_PCF_JTAG_TDO)>;
};
uarths_pinctrl: uarths-pinmux {
pinmux = <K210_FPIOA(4, K210_PCF_UARTHS_RX)>,
<K210_FPIOA(5, K210_PCF_UARTHS_TX)>;
};
spi0_pinctrl: spi0-pinmux {
pinmux = <K210_FPIOA(6, K210_PCF_GPIOHS20)>, /* cs */
<K210_FPIOA(7, K210_PCF_SPI0_SCLK)>, /* wr */
<K210_FPIOA(8, K210_PCF_GPIOHS21)>; /* dc */
};
dvp_pinctrl: dvp-pinmux {
pinmux = <K210_FPIOA(9, K210_PCF_SCCB_SCLK)>,
<K210_FPIOA(10, K210_PCF_SCCB_SDA)>,
<K210_FPIOA(11, K210_PCF_DVP_RST)>,
<K210_FPIOA(12, K210_PCF_DVP_VSYNC)>,
<K210_FPIOA(13, K210_PCF_DVP_PWDN)>,
<K210_FPIOA(14, K210_PCF_DVP_XCLK)>,
<K210_FPIOA(15, K210_PCF_DVP_PCLK)>,
<K210_FPIOA(17, K210_PCF_DVP_HSYNC)>;
};
gpiohs_pinctrl: gpiohs-pinmux {
pinmux = <K210_FPIOA(16, K210_PCF_GPIOHS0)>,
<K210_FPIOA(20, K210_PCF_GPIOHS4)>, /* Rot. dip sw line 8 */
<K210_FPIOA(21, K210_PCF_GPIOHS5)>, /* Rot. dip sw line 4 */
<K210_FPIOA(22, K210_PCF_GPIOHS6)>, /* Rot. dip sw line 2 */
<K210_FPIOA(23, K210_PCF_GPIOHS7)>, /* Rot. dip sw line 1 */
<K210_FPIOA(24, K210_PCF_GPIOHS8)>,
<K210_FPIOA(25, K210_PCF_GPIOHS9)>,
<K210_FPIOA(26, K210_PCF_GPIOHS10)>;
};
spi1_pinctrl: spi1-pinmux {
pinmux = <K210_FPIOA(29, K210_PCF_SPI1_SCLK)>,
<K210_FPIOA(30, K210_PCF_SPI1_D0)>,
<K210_FPIOA(31, K210_PCF_SPI1_D1)>,
<K210_FPIOA(32, K210_PCF_GPIOHS16)>; /* cs */
};
i2s0_pinctrl: i2s0-pinmux {
pinmux = <K210_FPIOA(33, K210_PCF_I2S0_IN_D0)>,
<K210_FPIOA(34, K210_PCF_I2S0_WS)>,
<K210_FPIOA(35, K210_PCF_I2S0_SCLK)>;
};
};
&uarths0 {
pinctrl-0 = <&uarths_pinctrl>;
pinctrl-names = "default";
status = "okay";
};
&gpio0 {
pinctrl-0 = <&gpiohs_pinctrl>;
pinctrl-names = "default";
status = "okay";
};
&i2s0 {
#sound-dai-cells = <1>;
pinctrl-0 = <&i2s0_pinctrl>;
pinctrl-names = "default";
};
&spi0 {
pinctrl-0 = <&spi0_pinctrl>;
pinctrl-names = "default";
num-cs = <1>;
cs-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
panel@0 {
compatible = "ilitek,ili9341";
reg = <0>;
dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
spi-max-frequency = <15000000>;
status = "disabled";
};
};
&spi1 {
pinctrl-0 = <&spi1_pinctrl>;
pinctrl-names = "default";
num-cs = <1>;
cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
status = "okay";
slot@0 {
compatible = "mmc-spi-slot";
reg = <0>;
voltage-ranges = <3300 3300>;
spi-max-frequency = <25000000>;
broken-cd;
};
};

+ 459
- 0
arch/riscv/boot/dts/canaan/k210.dtsi View File

@ -0,0 +1,459 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
* Copyright (C) 2020 Western Digital Corporation or its affiliates.
*/
#include <dt-bindings/clock/k210-clk.h>
#include <dt-bindings/pinctrl/k210-fpioa.h>
#include <dt-bindings/reset/k210-rst.h>
/ {
/*
* Although the K210 is a 64-bit CPU, the address bus is only 32-bits
* wide, and the upper half of all addresses is ignored.
*/
#address-cells = <1>;
#size-cells = <1>;
compatible = "canaan,kendryte-k210";
aliases {
serial0 = &uarths0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
};
/*
* The K210 has an sv39 MMU following the privileged specification v1.9.
* Since this is a non-ratified draft specification, the kernel does not
* support it and the K210 support enabled only for the !MMU case.
* Be consistent with this by setting the CPUs MMU type to "none".
*/
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <7800000>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "canaan,k210", "riscv";
reg = <0>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,none";
i-cache-block-size = <64>;
i-cache-size = <0x8000>;
d-cache-block-size = <64>;
d-cache-size = <0x8000>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "canaan,k210", "riscv";
reg = <1>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,none";
i-cache-block-size = <64>;
i-cache-size = <0x8000>;
d-cache-block-size = <64>;
d-cache-size = <0x8000>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
sram: memory@80000000 {
device_type = "memory";
compatible = "canaan,k210-sram";
reg = <0x80000000 0x400000>,
<0x80400000 0x200000>,
<0x80600000 0x200000>;
reg-names = "sram0", "sram1", "aisram";
clocks = <&sysclk K210_CLK_SRAM0>,
<&sysclk K210_CLK_SRAM1>,
<&sysclk K210_CLK_AI>;
clock-names = "sram0", "sram1", "aisram";
};
clocks {
in0: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
interrupt-parent = <&plic0>;
rom0: nvmem@1000 {
reg = <0x1000 0x1000>;
read-only;
};
clint0: timer@2000000 {
compatible = "canaan,k210-clint", "sifive,clint0";
reg = <0x2000000 0xC000>;
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
&cpu1_intc 3 &cpu1_intc 7>;
};
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
#address-cells = <0>;
compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
reg = <0xC000000 0x4000000>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
riscv,ndev = <65>;
};
uarths0: serial@38000000 {
compatible = "canaan,k210-uarths", "sifive,uart0";
reg = <0x38000000 0x1000>;
interrupts = <33>;
clocks = <&sysclk K210_CLK_CPU>;
};
gpio0: gpio-controller@38001000 {
#interrupt-cells = <2>;
#gpio-cells = <2>;
compatible = "canaan,k210-gpiohs", "sifive,gpio0";
reg = <0x38001000 0x1000>;
interrupt-controller;
interrupts = <34 35 36 37 38 39 40 41
42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57
58 59 60 61 62 63 64 65>;
gpio-controller;
ngpios = <32>;
};
dmac0: dma-controller@50000000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x50000000 0x1000>;
interrupts = <27 28 29 30 31 32>;
#dma-cells = <1>;
clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
clock-names = "core-clk", "cfgr-clk";
resets = <&sysrst K210_RST_DMA>;
dma-channels = <6>;
snps,dma-masters = <2>;
snps,priority = <0 1 2 3 4 5>;
snps,data-width = <5>;
snps,block-size = <0x200000 0x200000 0x200000
0x200000 0x200000 0x200000>;
snps,axi-max-burst-len = <256>;
};
apb0: bus@50200000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-pm-bus";
ranges;
clocks = <&sysclk K210_CLK_APB0>;
gpio1: gpio@50200000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0x50200000 0x80>;
clocks = <&sysclk K210_CLK_APB0>,
<&sysclk K210_CLK_GPIO>;
clock-names = "bus", "db";
resets = <&sysrst K210_RST_GPIO>;
gpio1_0: gpio-port@0 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "snps,dw-apb-gpio-port";
reg = <0>;
interrupt-controller;
interrupts = <23>;
gpio-controller;
ngpios = <8>;
};
};
uart1: serial@50210000 {
compatible = "snps,dw-apb-uart";
reg = <0x50210000 0x100>;
interrupts = <11>;
clocks = <&sysclk K210_CLK_UART1>,
<&sysclk K210_CLK_APB0>;
clock-names = "baudclk", "apb_pclk";
resets = <&sysrst K210_RST_UART1>;
reg-io-width = <4>;
reg-shift = <2>;
dcd-override;
dsr-override;
cts-override;
ri-override;
};
uart2: serial@50220000 {
compatible = "snps,dw-apb-uart";
reg = <0x50220000 0x100>;
interrupts = <12>;
clocks = <&sysclk K210_CLK_UART2>,
<&sysclk K210_CLK_APB0>;
clock-names = "baudclk", "apb_pclk";
resets = <&sysrst K210_RST_UART2>;
reg-io-width = <4>;
reg-shift = <2>;
dcd-override;
dsr-override;
cts-override;
ri-override;
};
uart3: serial@50230000 {
compatible = "snps,dw-apb-uart";
reg = <0x50230000 0x100>;
interrupts = <13>;
clocks = <&sysclk K210_CLK_UART3>,
<&sysclk K210_CLK_APB0>;
clock-names = "baudclk", "apb_pclk";
resets = <&sysrst K210_RST_UART3>;
reg-io-width = <4>;
reg-shift = <2>;
dcd-override;
dsr-override;
cts-override;
ri-override;
};
spi2: spi@50240000 {
compatible = "canaan,k210-spi";
spi-slave;
reg = <0x50240000 0x100>;
#address-cells = <0>;
#size-cells = <0>;
interrupts = <3>;
clocks = <&sysclk K210_CLK_SPI2>,
<&sysclk K210_CLK_APB0>;
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI2>;
spi-max-frequency = <25000000>;
};
i2s0: i2s@50250000 {
compatible = "snps,designware-i2s";
reg = <0x50250000 0x200>;
interrupts = <5>;
clocks = <&sysclk K210_CLK_I2S0>;
clock-names = "i2sclk";
resets = <&sysrst K210_RST_I2S0>;
};
i2s1: i2s@50260000 {
compatible = "snps,designware-i2s";
reg = <0x50260000 0x200>;
interrupts = <6>;
clocks = <&sysclk K210_CLK_I2S1>;
clock-names = "i2sclk";
resets = <&sysrst K210_RST_I2S1>;
};
i2s2: i2s@50270000 {
compatible = "snps,designware-i2s";
reg = <0x50270000 0x200>;
interrupts = <7>;
clocks = <&sysclk K210_CLK_I2S2>;
clock-names = "i2sclk";
resets = <&sysrst K210_RST_I2S2>;
};
i2c0: i2c@50280000 {
compatible = "snps,designware-i2c";
reg = <0x50280000 0x100>;
interrupts = <8>;
clocks = <&sysclk K210_CLK_I2C0>,
<&sysclk K210_CLK_APB0>;
clock-names = "ref", "pclk";
resets = <&sysrst K210_RST_I2C0>;
};
i2c1: i2c@50290000 {
compatible = "snps,designware-i2c";
reg = <0x50290000 0x100>;
interrupts = <9>;
clocks = <&sysclk K210_CLK_I2C1>,
<&sysclk K210_CLK_APB0>;
clock-names = "ref", "pclk";
resets = <&sysrst K210_RST_I2C1>;
};
i2c2: i2c@502a0000 {
compatible = "snps,designware-i2c";
reg = <0x502A0000 0x100>;
interrupts = <10>;
clocks = <&sysclk K210_CLK_I2C2>,
<&sysclk K210_CLK_APB0>;
clock-names = "ref", "pclk";
resets = <&sysrst K210_RST_I2C2>;
};
fpioa: pinmux@502b0000 {
compatible = "canaan,k210-fpioa";
reg = <0x502B0000 0x100>;
clocks = <&sysclk K210_CLK_FPIOA>,
<&sysclk K210_CLK_APB0>;
clock-names = "ref", "pclk";
resets = <&sysrst K210_RST_FPIOA>;
canaan,k210-sysctl-power = <&sysctl 108>;
};
timer0: timer@502d0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502D0000 0x100>;
interrupts = <14 15>;
clocks = <&sysclk K210_CLK_TIMER0>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
resets = <&sysrst K210_RST_TIMER0>;
};
timer1: timer@502e0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502E0000 0x100>;
interrupts = <16 17>;
clocks = <&sysclk K210_CLK_TIMER1>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
resets = <&sysrst K210_RST_TIMER1>;
};
timer2: timer@502f0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502F0000 0x100>;
interrupts = <18 19>;
clocks = <&sysclk K210_CLK_TIMER2>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
resets = <&sysrst K210_RST_TIMER2>;
};
};
apb1: bus@50400000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-pm-bus";
ranges;
clocks = <&sysclk K210_CLK_APB1>;
wdt0: watchdog@50400000 {
compatible = "snps,dw-wdt";
reg = <0x50400000 0x100>;
interrupts = <21>;
clocks = <&sysclk K210_CLK_WDT0>,
<&sysclk K210_CLK_APB1>;
clock-names = "tclk", "pclk";
resets = <&sysrst K210_RST_WDT0>;
};
wdt1: watchdog@50410000 {
compatible = "snps,dw-wdt";
reg = <0x50410000 0x100>;
interrupts = <22>;
clocks = <&sysclk K210_CLK_WDT1>,
<&sysclk K210_CLK_APB1>;
clock-names = "tclk", "pclk";
resets = <&sysrst K210_RST_WDT1>;
};
sysctl: syscon@50440000 {
compatible = "canaan,k210-sysctl",
"syscon", "simple-mfd";
reg = <0x50440000 0x100>;
clocks = <&sysclk K210_CLK_APB1>;
clock-names = "pclk";
sysclk: clock-controller {
#clock-cells = <1>;
compatible = "canaan,k210-clk";
clocks = <&in0>;
};
sysrst: reset-controller {
compatible = "canaan,k210-rst";
#reset-cells = <1>;
};
reboot: syscon-reboot {
compatible = "syscon-reboot";
regmap = <&sysctl>;
offset = <48>;
mask = <1>;
value = <1>;
};
};
};
apb2: bus@52000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-pm-bus";
ranges;
clocks = <&sysclk K210_CLK_APB2>;
spi0: spi@52000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "canaan,k210-spi";
reg = <0x52000000 0x100>;
interrupts = <1>;
clocks = <&sysclk K210_CLK_SPI0>,
<&sysclk K210_CLK_APB2>;
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI0>;
reset-names = "spi";
spi-max-frequency = <25000000>;
num-cs = <4>;
reg-io-width = <4>;
};
spi1: spi@53000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "canaan,k210-spi";
reg = <0x53000000 0x100>;
interrupts = <2>;
clocks = <&sysclk K210_CLK_SPI1>,
<&sysclk K210_CLK_APB2>;
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI1>;
reset-names = "spi";
spi-max-frequency = <25000000>;
num-cs = <4>;
reg-io-width = <4>;
};
spi3: spi@54000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwc-ssi-1.01a";
reg = <0x54000000 0x200>;
interrupts = <4>;
clocks = <&sysclk K210_CLK_SPI3>,
<&sysclk K210_CLK_APB2>;
clock-names = "ssi_clk", "pclk";
resets = <&sysrst K210_RST_SPI3>;
reset-names = "spi";
/* Could possibly go up to 200 MHz */
spi-max-frequency = <100000000>;
num-cs = <4>;
reg-io-width = <4>;
};
};
};
};

+ 46
- 0
arch/riscv/boot/dts/canaan/k210_generic.dts View File

@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
* Copyright (C) 2020 Western Digital Corporation or its affiliates.
*/
/dts-v1/;
#include "k210.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Kendryte K210 generic";
compatible = "canaan,kendryte-k210";
chosen {
bootargs = "earlycon console=ttySIF0";
stdout-path = "serial0:115200n8";
};
};
&fpioa {
pinctrl-0 = <&jtag_pins>;
pinctrl-names = "default";
status = "okay";
jtag_pins: jtag-pinmux {
pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
<K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
<K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
<K210_FPIOA(3, K210_PCF_JTAG_TDO)>;
};
uarths_pins: uarths-pinmux {
pinmux = <K210_FPIOA(4, K210_PCF_UARTHS_RX)>,
<K210_FPIOA(5, K210_PCF_UARTHS_TX)>;
};
};
&uarths0 {
pinctrl-0 = <&uarths_pins>;
pinctrl-names = "default";
status = "okay";
};

+ 209
- 0
arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts View File

@ -0,0 +1,209 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
* Copyright (C) 2020 Western Digital Corporation or its affiliates.
*/
/dts-v1/;
#include "k210.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "SiPeed MAIX BiT";
compatible = "sipeed,maix-bit", "sipeed,maix-bitm",
"canaan,kendryte-k210";
chosen {
bootargs = "earlycon console=ttySIF0";
stdout-path = "serial0:115200n8";
};
gpio-leds {
compatible = "gpio-leds";
led0 {
color = <LED_COLOR_ID_GREEN>;
label = "green";
gpios = <&gpio1_0 4 GPIO_ACTIVE_LOW>;
};
led1 {
color = <LED_COLOR_ID_RED>;
label = "red";
gpios = <&gpio1_0 5 GPIO_ACTIVE_LOW>;
};
led2 {
color = <LED_COLOR_ID_BLUE>;
label = "blue";
gpios = <&gpio1_0 6 GPIO_ACTIVE_LOW>;
};
};
gpio-keys {
compatible = "gpio-keys";
boot {
label = "BOOT";
linux,code = <BTN_0>;
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
};
};
};
&fpioa {
pinctrl-names = "default";
pinctrl-0 = <&jtag_pinctrl>;
status = "okay";
jtag_pinctrl: jtag-pinmux {
pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
<K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
<K210_FPIOA(2, K210_PCF_JTAG_TMS)>,